1. Field of the Invention
A method for transmitting a power-saving command between a computer system and system chips thereof, a power-mode command is introduced into a first system chip for communicating with the computer system so as to drive the peripheral device into a power-saving mode.
2. Description of Related Art
The components and the peripherals of a computer system perform through the signal transmission via a bus transmitting the digital data with each other. The bus, such as a peripheral component interconnect (PCI) bus, accelerated graphics port (AGP) or the like, is used for transmitting data. The signal or data transmission between a central processing unit (CPU) and a North/South Bridge chip or the system memory is through a specific bus, thereby either do the plurality of peripherals or the components coupled to the bus.
Reference is made to FIG. 1 showing the conventional PCI bus 16 of a computer system is used to couple with a plurality of peripheral devices a, b, c. Under a low-power mode of the computer system, a PCI special cycle performs as the CPU 10 receives a low-power instruction via the PCI bus 16 controlled by the North or South Bridge chip 11, 12. After that, the peripheral devices a, b, c enter a predetermined state in the low-power mode controlled by a BIOS (basic I/O system) 15, or even to transmit the low-power instruction to the system memory 13 or graphic chip 14 via the specific bus.
U.S. Pat. No. 6,357,013 discloses a plurality of low-power instructions transmitted via the PCI bus in a computer system. In view of the conventional PCI bus, every peripheral coupled to PCI bus shares a 133 MB/sec bandwidth merely provided by a main channel for transmitting data to the South Bridge chip. Since the above-mentioned signal transmission via the PCI bus is set in timely order, if big data is under the transmission, the transmitting rate therefore will be slow down. For example, if a new-development serial ATA (SATA) device or a gigabit-level network device couples to the conventional PCI bus, the efficiency of the transmission thereof will be reduced due to the insufficient bandwidth.
Different from the current PCI standard using a multi-drop technology, a PCI-Express standard introduces a switch point-to-point transmission technology. The physical layer of the PCI-Express bus has a set of single-tasking lane composed of a transmit terminal and a receive terminal, moreover, each PCI-Express bus uses its own lane to communicate with the South Bridge chip independently. Since no more the common bus structure but independent lane used for the PCI-Express bus, the interference under the data transmission can be excluded. Furthermore, each data under the PCI-Express standard has the first privilege of the transmission, therefore the PCI-Express will be the first choice used in the computer system.
The PCI-Express standard defines a L2 and L3 power mode used for supplying power to the peripherals. Wherein, the L2 power mode indicates a main power and a reference clock are removed except for an auxiliary power, so the computer system enters a lowest power consuming condition and the system still can be woken up anytime. The L3 power mode indicates the main power and the reference clock are removed without the provision of the auxiliary power, the computer system will not be resumed until it reboots.
In the prior arts, a power-saving mode of the computer system is initialized after some steps for signal communication between the CPU and the South Bridge chip, the L2 and L3 power modes are defined. Then, an OS direct power management (OSPM) in the system initialize the peripheral devices ready into the power-saving mode. Meanwhile, an advanced configuration and power interface (ACPI) installed in the South Bridge chip will notify the PCI-Express peripheral devices that are ready into the power-saving mode. Otherwise, the prior arts never consider how to make the peripheral devices coupled with the North Bridge chip enter the power-saving mode via the PCI-Express bus smoothly.